1. Field of the Invention
The present invention relates to an analog-digital converter that converts an analog signal to a digital signal.
2. Description of Related Art
In recent years, an analog-digital converter (ADC) that converts an analog signal to a digital signal has been used in various fields. FIG. 3 shows V-F (Voltage to Frequency) type of ADC disclosed in Japanese Unexamined Patent Application Publication No. 2007-139700.
As shown in FIG. 3, a voltage-pulse converter 100 includes an input switching circuit 104, an integrator output inductive unit 105 as a voltage inductive unit, an integrator 108, first and second comparators 112 and 113 (window comparator), an RS latch circuit 114, first and second integrator output error detecting circuits 116, 119, first and second comparator continuous output judgment circuits 117, 118, and a flip-flop FF 123 as a flag output unit.
Now, the input switching circuit 104 switches connection between a CS positive terminal and a CS negative terminal and a positive or negative input terminal of the integrator 108. Further, the integrator 108 includes a differential amplifier 111, a resistor 109 having one end connected with a negative terminal (inverting input terminal) of the differential amplifier 111, and a capacitor 110 connected between an output of the differential amplifier 111 and a negative terminal thereof.
The integrator output inductive unit 105 includes switches 106 and 107 having one end connected to nodes 106a and 106b, respectively, and having the other end set to a reference potential. The integrator output inductive unit 105 leads the output of the integrator 108 to around first or second detection voltage.
The first and second comparators 112 and 113 detect from the output of the integrator 108 a first detection voltage (1 V) and a second detection voltage (2 V) which is higher than the first detection voltage.
The FF 123 outputs a flag FLAG based on the comparison result in the first and second comparators 112 and 113. Further, an inverter 124 outputs an output signal CKOUT having frequency according to the input voltage.
According to such an operation, the circuit shown in FIG. 3 converts the input voltage generated between the CS positive terminal 101 and the CS negative terminal 102 to the pulse. The input switching circuit 104 switches the connection based on the flag FLAG and the output signal CKOUT.
Further, the circuit shown in FIG. 3 includes an error detecting circuit 116 that generates an integrator output error signal E-H when an output voltage of the integrator 108 is higher than high-potential side reference detection voltage (2 V) for at least a predetermined period of time. When the integrator output voltage error signal E-H is input to an OR circuit 120, the OR circuit 120 outputs a signal OUT120 to the integrator output inductive unit 105. Upon receiving the signal OUT 120, the integrator output inductive unit 105 turns on the switch 106, so as to lead the output voltage of the integrator to the potential that is lower than the high-potential side reference detection voltage (2 V).
Similarly, the circuit shown in FIG. 3 includes an error detecting circuit 119 that generates an integrator output error signal E-L when the output voltage of the integrator 108 is lower than low-potential side reference detection voltage (1 V) for at least a predetermined period of time. When the integrator output voltage error signal E-L is input to an OR circuit 122, the OR circuit 122 outputs a signal OUT122 to the integrator output inductive unit 105. Upon receiving the signal OUT122, the integrator output inductive unit 105 turns on the switch 107, so as to lead the output voltage of the integrator to the potential that is higher than the low-potential side reference detection voltage (1 V).